1. Field of the Invention
The present invention relates to a technology for separating a data sample having a desired number of bits therein from a data bit stream which is to be inputted into an audio decoder or a digital signal processor, and more particularly to an improved bit stream parsing apparatus for an audio decoder which makes it possible to employ a load and parallel shift technique in order to separate samples during a single clock cycle.
2. Description of the Background Art
FIG. 1 is a block diagram extracted from U.S. Pat. No. 5,644,310 of "Integrated Audio Decoder System and Method of Operation", wherein portions concerned with the accompanying description of the present invention are data register 114, shift counter 128, load shift counter 130, data shifter 126, accumulator 110, and execution control state machine 104.
Therein, the data shifter 126 provides N-bit data sequentially to the accumulator 110 under the control of the shift counter 128. The accumulator 110 accumulates the N-bit data applied thereto, and the accumulated data are transferred through the multiplexer 124 to the data bus. Also, the shifter counter 128 is controlled by the execution control state machine 104.
The 6-bit load shift counter 130 which is controlled by the execution control state machine 104 checks up how many bits of data are transferred from the data shifter 126 to the accumulator 110. A count value counted by the load shift counter 130 is transferred through the multiplexer 124 to the data bus.
In order to obtain an N-bit data sample from a bit stream, the execution control state machine 104 checks up the state of the load shift counter 130 at each clock cycle and confirms if the count value in the load shift counter 130 is "N".
When a new sample having N-bit data is transferred to the accumulator 110, the count value becomes "N", and at this time the value accumulated in the accumulator 110 becomes transferred through the data bus to a memory.
Therefore, it takes N cycles to obtain an N-bit data sample.
In such a conventional bit stream parsing apparatus, there is employed a load and serial shift technique to process the bit stream and it takes N cycles to obtain an N-bit sample, thereby deteriorating its process rate.